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Si3460-EVB
4. PSE Detection, Classification, Power-Up, and Power Removal
The basic sequence for applying power is shown in Figure 3. Following is a description of the functions that must
be performed in each phase.
57 V
44 V
20.5 V
15.5 V
10 V
2.8 V
Time
Detection
Classification
Apply Power
Turn off
Figure 3. Detection, Classification, Powerup, and Disconnect Sequence
4.1. Detection
During the detection phase, the PSE probes with limited current and voltage to determine if a 25 k ? signature is
present. A valid PD must present between 23.75 and 26.25 k ? in the range of 2.7 to 10.1 V, with an offset (due to
the bridge diodes) of up to 1.9 V, and a parallel capacitance of between 0.05 and 0.12 μF. An IEEE-compliant PSE
probes 2.8 and 10 V, with at least a 1 V step and current limit of <5 mA. The PSE must accept signatures in the
range of 19–26.5 k ? with capacitance of up to 0.15 μF and must reject resistance <15 k ? or >33 k ? as well as
capacitive signatures >10 μF.
The strict limits on the detection phase ensure that non PoE enabled devices are not inadvertently powered. For
endpoint applications, detection must be completed within 500 ms of applying a valid signature. When configured
as a midspan there is a possibility that the PSE circuit will compete with an endpoint PSE, and, as required by the
IEEE specifications, the Si3460 is therefore required to wait at least 2 seconds after an unsuccessful detection
cycle to repeat the detection process.
Rev. 1.2
3
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